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<div class="header">
  <div class="summary">
<a href="#define-members">Macros</a>  </div>
  <div class="headertitle">
<div class="title">UART RX FIFO status.<div class="ingroups"><a class="el" href="group__group__scb.html">SCB          (Serial Communication Block)</a> &raquo; <a class="el" href="group__group__scb__uart.html">UART (SCB)</a> &raquo; <a class="el" href="group__group__scb__uart__macros.html">Macros</a></div></div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p>Macros to check UART RX FIFO status returned by <a class="el" href="group__group__scb__uart__low__level__functions.html#gaa2d783e45d8b8a9803bb5b667d71f3b9">Cy_SCB_UART_GetRxFifoStatus</a> function or assign mask for <a class="el" href="group__group__scb__uart__low__level__functions.html#ga3f1e6aa6e686a215ab03b5d264510b3f">Cy_SCB_UART_ClearRxFifoStatus</a> function. </p>
<p>Each UART RX FIFO status is encoded in a separate bit, therefore multiple bits may be set to indicate the current status. </p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga2c2ad72882685c29a4755ead9e5bcda9"><td class="memItemLeft" align="right" valign="top"><a id="ga2c2ad72882685c29a4755ead9e5bcda9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__uart__macros__rx__fifo__status.html#ga2c2ad72882685c29a4755ead9e5bcda9">CY_SCB_UART_RX_TRIGGER</a>&#160;&#160;&#160;(SCB_INTR_RX_TRIGGER_Msk)</td></tr>
<tr class="memdesc:ga2c2ad72882685c29a4755ead9e5bcda9"><td class="mdescLeft">&#160;</td><td class="mdescRight">The number of entries in the RX FIFO is more than the RX FIFO trigger level value. <br /></td></tr>
<tr class="separator:ga2c2ad72882685c29a4755ead9e5bcda9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae22bfd5f13fbb141ec2f139c178a6cfd"><td class="memItemLeft" align="right" valign="top"><a id="gae22bfd5f13fbb141ec2f139c178a6cfd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__uart__macros__rx__fifo__status.html#gae22bfd5f13fbb141ec2f139c178a6cfd">CY_SCB_UART_RX_NOT_EMPTY</a>&#160;&#160;&#160;(SCB_INTR_RX_NOT_EMPTY_Msk)</td></tr>
<tr class="memdesc:gae22bfd5f13fbb141ec2f139c178a6cfd"><td class="mdescLeft">&#160;</td><td class="mdescRight">The RX FIFO is not empty, there is data to read. <br /></td></tr>
<tr class="separator:gae22bfd5f13fbb141ec2f139c178a6cfd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaabd8566f82db4ca907b902c33d8610b0"><td class="memItemLeft" align="right" valign="top"><a id="gaabd8566f82db4ca907b902c33d8610b0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__uart__macros__rx__fifo__status.html#gaabd8566f82db4ca907b902c33d8610b0">CY_SCB_UART_RX_FULL</a>&#160;&#160;&#160;(SCB_INTR_RX_FULL_Msk)</td></tr>
<tr class="memdesc:gaabd8566f82db4ca907b902c33d8610b0"><td class="mdescLeft">&#160;</td><td class="mdescRight">The RX FIFO is full, there is no more space for additional data, and any additional data will be dropped. <br /></td></tr>
<tr class="separator:gaabd8566f82db4ca907b902c33d8610b0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga756096145d4da064bb6ef14344923cd8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__uart__macros__rx__fifo__status.html#ga756096145d4da064bb6ef14344923cd8">CY_SCB_UART_RX_OVERFLOW</a>&#160;&#160;&#160;(SCB_INTR_RX_OVERFLOW_Msk)</td></tr>
<tr class="memdesc:ga756096145d4da064bb6ef14344923cd8"><td class="mdescLeft">&#160;</td><td class="mdescRight">The RX FIFO was full and there was an attempt to write to it.  <a href="#ga756096145d4da064bb6ef14344923cd8">More...</a><br /></td></tr>
<tr class="separator:ga756096145d4da064bb6ef14344923cd8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8875bbc01ed5bff5e6d31c5653635cf3"><td class="memItemLeft" align="right" valign="top"><a id="ga8875bbc01ed5bff5e6d31c5653635cf3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__uart__macros__rx__fifo__status.html#ga8875bbc01ed5bff5e6d31c5653635cf3">CY_SCB_UART_RX_UNDERFLOW</a>&#160;&#160;&#160;(SCB_INTR_RX_UNDERFLOW_Msk)</td></tr>
<tr class="memdesc:ga8875bbc01ed5bff5e6d31c5653635cf3"><td class="mdescLeft">&#160;</td><td class="mdescRight">An attempt to read from an empty RX FIFO. <br /></td></tr>
<tr class="separator:ga8875bbc01ed5bff5e6d31c5653635cf3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2b72cda1727aaa447c0820ec971452a1"><td class="memItemLeft" align="right" valign="top"><a id="ga2b72cda1727aaa447c0820ec971452a1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__uart__macros__rx__fifo__status.html#ga2b72cda1727aaa447c0820ec971452a1">CY_SCB_UART_RX_ERR_FRAME</a>&#160;&#160;&#160;(SCB_INTR_RX_FRAME_ERROR_Msk)</td></tr>
<tr class="memdesc:ga2b72cda1727aaa447c0820ec971452a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">The RX FIFO detected a frame error, either a stop or stop-bit error. <br /></td></tr>
<tr class="separator:ga2b72cda1727aaa447c0820ec971452a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa64782b6ba31e4b36c5ff9a74b42219b"><td class="memItemLeft" align="right" valign="top"><a id="gaa64782b6ba31e4b36c5ff9a74b42219b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__uart__macros__rx__fifo__status.html#gaa64782b6ba31e4b36c5ff9a74b42219b">CY_SCB_UART_RX_ERR_PARITY</a>&#160;&#160;&#160;(SCB_INTR_RX_PARITY_ERROR_Msk)</td></tr>
<tr class="memdesc:gaa64782b6ba31e4b36c5ff9a74b42219b"><td class="mdescLeft">&#160;</td><td class="mdescRight">The RX FIFO detected a parity error. <br /></td></tr>
<tr class="separator:gaa64782b6ba31e4b36c5ff9a74b42219b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga305036745f5db0cea8cd97fa8b6ade43"><td class="memItemLeft" align="right" valign="top"><a id="ga305036745f5db0cea8cd97fa8b6ade43"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__uart__macros__rx__fifo__status.html#ga305036745f5db0cea8cd97fa8b6ade43">CY_SCB_UART_RX_BREAK_DETECT</a>&#160;&#160;&#160;(SCB_INTR_RX_BREAK_DETECT_Msk)</td></tr>
<tr class="memdesc:ga305036745f5db0cea8cd97fa8b6ade43"><td class="mdescLeft">&#160;</td><td class="mdescRight">The RX FIFO detected a break transmission from the transmitter. <br /></td></tr>
<tr class="separator:ga305036745f5db0cea8cd97fa8b6ade43"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="ga756096145d4da064bb6ef14344923cd8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga756096145d4da064bb6ef14344923cd8">&#9670;&nbsp;</a></span>CY_SCB_UART_RX_OVERFLOW</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_SCB_UART_RX_OVERFLOW&#160;&#160;&#160;(SCB_INTR_RX_OVERFLOW_Msk)</td>
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</div><div class="memdoc">

<p>The RX FIFO was full and there was an attempt to write to it. </p>
<p>That additional data was dropped. </p>

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